It is well known that there is an continuing trend towards micro-miniaturization in the electronic arts. A significant obstacle to micro-miniaturization is the size of integrated circuit (IC) chip carriers. Conventional IC chip carriers have utilized a rigid substrate for mounting the integrated circuit chip, and have been limited to a minimum line width and spacing, e.g., 4 mils (0.1016 mm) and 3 mils (0.0762 mm), respectively, for interconnect paths, based upon obtaining reasonable manufacturing yields. Rigid substrates have been further limited to a minimum diameter-plus-tolerance, e.g., 20 mils (0.508 mm), for holes drilled to provide interconnection "vias" from the top surface of the substrate to the bottom surface. These limitations in minimum line width and spacing, and in minimum space required for "vias", have limited the conventional IC chip carrier to a maximum mounting pad density characterized by a forty-five mil (1.143 mm) center-to-center spacing, or "pitch" between individual pads. This maximum mounting pad density has forced the IC chip carrier to be substantially larger than otherwise would be necessary to accommodate the IC itself without considering the mounting pad array.
Thus, what is needed is an IC chip carrier that overcomes the conventional limitations of line width and spacing, and of space required for "vias", in order to achieve a substantial increase in mounting pad density to reduce the size of the chip carrier, thereby permitting a next step in the continuing micro-miniaturization trend.